1. Field of the Invention
The present invention is directed toward the field of memory signaling circuits, and more particularly to a programmable data buffer circuit and a programmable clock generator circuit.
2. Art Background
Many memory signal distribution methods rely on clock generation and data buffering integrated circuits (IC). A typical application for such ICs is a registered dual inline memory module (DIMM) 100, as shown in FIG. 1. The memory module input clock is fed to a phase-locked loop (PLL) based IC. The PLL-based IC 110 receives the input clock on a clock input 111. PLL-based IC 110 outputs a plurality of clocks to the DRAM ICs 130-1 to 130-N, and to the register IC 120. Both the DRAM and register ICs are mounted on the memory module. The register receives data input 121 and outputs a plurality of data signals to the DRAM ICs 130-1 to 130-N.
A given IC design, for either register or clock, is often sold for use in a variety of memory module configurations. This requires that the IC be able to drive signals to a variable number of memory ICs, depending on the implementation. Current designs must sacrifice precision for this versatility, driving a set of memory ICs at a signal strength that fails to optimize for either quality or speed.
What is needed is a method and/or device that permits tuning of signaling strength to implementation details in an economical fashion.
Further, what is needed is a method and/or device that, even when designed on a per-system or per-system basis, permits tuning at the per-lot level.